Issue No. 04 - July/August (2011 vol. 28)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2011.25
Shyue-Kung Lu , Nat. Taiwan Univ. of Sci. & Technol., Taipei, Taiwan
Shi-Yu Huang , Nat. Tsing Hua Univ., Hsinchu, Taiwan
Cheng-Wen Wu , Nat. Tsing Hua Univ., Hsinchu, Taiwan
Yin-Mou Chen , Fu-Jen Catholic Univ., Taipei, Taiwan
This article proposes a new approach for an FPGA-based emulation system for IC fault diagnosis that incorporates three speedup techniques: circuit partitioning, fault-injection elements (using a novel design), and a fault-injection scan chain. Experimental results in terms of hardware overhead and emulation time for ISCAS-85 benchmark circuits are compared with previous works to highlight the 33× speedup and 44% reduced overhead of this proposed system.
logic testing, fault diagnosis, field programmable gate arrays, integrated circuit testing, fault-injection scan chain, emulation-based diagnosis technique, logic cores, FPGA-based emulation system, IC fault diagnosis, circuit partitioning, fault-injection element, Circuit faults, Emulation, Fault diagnosis, Logic gates, Benchmark testing, Field programmable gate arrays, fault-injection scan chain, design and test, logic diagnosis, fault emulation, fault injection, circuit partitioning
Cheng-Wen Wu, Yin-Mou Chen, Shi-Yu Huang and Shyue-Kung Lu, "Speeding Up Emulation-Based Diagnosis Techniques for Logic Cores," in IEEE Design & Test of Computers, vol. 28, no. , pp. 88-97, 2011.