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Issue No. 04 - July/August (2011 vol. 28)
ISSN: 0740-7475
pp: 18-27
Florent de Dinechin , Ecole Normale Superieure de Lyon
Bogdan Pasca , Ecole Normale Superieure de Lyon
<p><it>Editor's note:</it></p><p>Efficient implementation of basic, data-path circuit elements is of fundamental importance to achieving high performance in FPGA-based acceleration of scientific computing. This work presents a leading effort to automate the production of pipelined data-path circuits for implementing numerical functions.</p><p align="right"><it>&#x2014;George A. Constantinides (Imperial College London) and Nicola Nicolici (McMaster University)</it></p>
design and test, FloPoCo, core generator, arithmetic circuit, floating-point, pipelining, data path, FPGAs, reconfigurable computing, VHDL, C&#x002B;&#x002B; framework

F. de Dinechin and B. Pasca, "Designing Custom Arithmetic Data Paths with FloPoCo," in IEEE Design & Test of Computers, vol. 28, no. , pp. 18-27, 2011.
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