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Issue No. 03 - May/June (2011 vol. 28)
ISSN: 0740-7475
pp: 32-43
Marius Gligor , Grenoble Institute of Technology
Patrice Gerin , Kalray
Mian-Muhammed Hamayun , Grenoble Institute of Technology
Hao Shen , Grenoble Institute of Technology
Frédéric Pétrot , Grenoble Institute of Technology
<p>Editor's note:</p><p>This article presents a wide variety of techniques for realizing transaction-level models of the increasingly large-scale multiprocessor systems on chip. It describes how such models of hardware allow subsequent software integration and system performance evaluation.</p><p align="right"><it>&#x2014;Zeljko Zilic, McGill University</it></p>
design and test, hardware-software simulation, MPSoC modeling, software simulation, performance estimation, code interpretation, native simulation
Marius Gligor, Nicolas Fournel, Patrice Gerin, Mian-Muhammed Hamayun, Hao Shen, Frédéric Pétrot, "On MPSoC Software Execution at the Transaction Level", IEEE Design & Test of Computers, vol. 28, no. , pp. 32-43, May/June 2011, doi:10.1109/MDT.2010.118
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