Issue No. 03 - May/June (2011 vol. 28)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2011.62
Prabhat Mishra , University of Florida
Zeljko Zilic , McGill University
Sandeep Shukla , Virginia Tech
<p>This issue of <it>IEEE Design and Test</it> presents four special-theme articles that highlight challenges and recent trends of multicore architecture validation using transaction-level models. The articles cover theoretical as well as practical aspects related to high-level validation including transaction-level modeling of multicore architectures, validation, and debug of TLM models, and industrial case studies.</p>
design and test, multicore architectures, transaction-level models, transaction-level modeling, validation
S. Shukla, P. Mishra and Z. Zilic, "Guest Editors' Introduction: Multicore SoC Validation with Transaction-Level Models," in IEEE Design & Test of Computers, vol. 28, no. , pp. 6-9, 2011.