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Issue No. 02 - March-April (2011 vol. 28)
ISSN: 0740-7475
pp: 16-29
Luciano Ost , LIRMM
Leandro Soares Indrusiak , University of York
Sanna Määttä , Tampere University of Technology
ABSTRACT
<p>This model-based methodology and supporting toolset lets designers estimate application-specific network-on-chip (NoC) power dissipation at early stages of the design flow. An actor-oriented simulation framework captures the NoC's dynamic behavior and feeds its parameters to a rate-based power estimation model. Integrating this model into the proposed design flow enables the analysis of different design parameters and the identification of the most power-efficient application platform mappings.</p>
INDEX TERMS
design and test, NoC power estimation model, MPSoC, SoC, NoC, actor orientation
CITATION

L. S. Indrusiak, L. Ost, F. G. Moraes, G. M. Guindani and S. Määttä, "Exploring NoC-Based MPSoC Design Space with Power Estimation Models," in IEEE Design & Test of Computers, vol. 28, no. , pp. 16-29, 2010.
doi:10.1109/MDT.2010.116
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