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Issue No. 01 - January/February (2011 vol. 28)
ISSN: 0740-7475
pp: 22-31
Yih Wang , Intel
Pramod Kolar , Intel
Liqiong Wei , Intel
Yong-Gee Ng , Intel
Kevin Zhang , Intel
<p>Editor's note:</p><p>Six-transistor SRAM cells have served as the workhorse embedded memory for several decades. However, with aggressive technology scaling, designers find it increasingly difficult to guarantee robust operation at low voltages because of the worsening process variation. This article presents circuit techniques pursued by industry to overcome SRAM scaling challenges in future technology nodes.</p><p align="right">&#x2014;Chris H. Kim, University of Minnesota</p>
design and test, SRAM, minimum operating voltage, VCCmin, low power, high-performance applications

U. Bhattacharya et al., "Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design," in IEEE Design & Test of Computers, vol. 28, no. , pp. 22-31, 2011.
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