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Guest Editors' Introduction: Nanoscale Memories Pose Unique Challenges

Chris H. Kim, University of Minnesota
Leland Chang, IBM T.J. Watson Research Center

Pages: pp. 6-8

Abstract—This special issue presents seven articles that examine the characteristics, capabilities, and challenges of various embedded memories, especially those designed in emerging technologies. The articles address the intricacies and trade-offs required by designers when faced with scaling and power constraints.

Keywords—design and test, embedded memories, PCRAM, SRAM, DRAM, eDRAM, FeRAM, MRAM, STT-RAM

Power dissipation has become the chief performance limitation in modern microprocessors, thus triggering a flurry of research activities on low-power design techniques. One of the most effective ways to curb chip power is to integrate larger cache memories to improve microarchitectural performance at only a modest increase in CV2f power. As a result, the past decade has seen a precipitous increase in the amount of on-die embedded memory. In state-of-the-art designs, approximately half the chip area can be devoted to cache memory. For example, Intel's 8-core Nehalem processor has 24 Mbytes of shared L3 cache based on SRAM cells, while IBM's Power7 processor has a 32-Mbyte L3 cache built in an embedded DRAM (eDRAM) technology. The need for robust, high-density embedded memories is projected to grow as designers continue to seek power-conscious ways to improve chip performance. The unique challenges and opportunities associated with embedded memory design make it an important area of research in extremely scaled technologies.

From the circuit designer's viewpoint, embedded memory presents unique challenges as compared with logic circuits. In particular, memory bit cell functionality is often inherently susceptible to various noise margin issues. For example, the read and write operations of 6-transistor SRAM cells are "ratioed" by nature, which diminishes voltage margins at low supply voltages. Likewise, 1-transistor, 1-capacitor eDRAM cells rely on the charge sharing to perform a read operation, which results in exposure to noise coupling, sense amplifier offsets, and other signal-margin–related problems. Memory density needs drive the use of minimally sized devices, which have significantly higher local mismatch, and tend to exacerbate these noise margin problems. To combat these issues, a tight coupling between process development, and memory circuit and architecture design, is indispensible. Device parameters are constantly adjusted to improve SRAM yield while the circuit design is optimized based on these new process parameters. Similarly, eDRAM circuit performance depends heavily on the characteristics of the specialized trench capacitors and access transistors. Emerging memory devices such as magnetic RAM (MRAM) and phase-change RAM (PCRAM), which have made great strides in recent years to become strong contenders against incumbent memories, present new trade-offs that further emphasize the need for a holistic, cross-disciplinary evaluation.

This special issue includes seven articles that will cover recent trends and innovative design solutions for various types of embedded memory. To provide a well-rounded view, we have selected articles on state-of-the-art mainstream memory such as eDRAM and SRAM as well as on emerging technologies such as MRAM, PCRAM, and resistive RAM (RRAM). Contributions to this special issue were made by researchers from both industry and academia to provide a practical yet forward-looking view of the present and future embedded memory landscape.

The special issue starts with a perspectives article, "Embedded Memories: Progress and a Look into the Future" by Kiyoo Itoh, an industry veteran and expert in memory device and circuit technology. This article is a concise tutorial on the evolution of existing memory technologies (SRAM, DRAM, and flash) and highlights the progress of emerging memories (MRAM, PCRAM, RRAM, and FeRAM). The article ends on an optimistic note by observing that disruptive new devices on the horizon might allow us to continue the historical rate of progress.

The second article, "Embedded DRAM in 45-nm Technology and Beyond" by Darren Anand and colleagues from IBM, discusses the latest design architecture and challenges related to developing embedded DRAM. Integrating DRAM technology with a high-performance logic process enables higher bit cell densities than traditional SRAM to improve system-level performance. Recent trends toward an in-system BIST and BISR architecture for improving eDRAM reliability and serviceability are also presented.

The next two articles discuss SRAM, which has been the industry's workhorse embedded memory for several decades due to its excellent logic compatibility and high performance. In "Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design," Fatih Hamzaoglu and colleagues from Intel's Advanced Design Group present their latest developments on SRAM circuits and process optimization for high-volume microprocessor products. These techniques enable the achievement of high-yield, high-performance SRAM designs while continuing to lower the minimum operating voltage in the presence of process variation. In the next article, "Challenges and Directions for Low-Voltage SRAM," Masood Qazi and colleagues from Massachusetts Institute of Technology present techniques to push this challenge further. Here, SRAM designs are reviewed for ultra-low-voltage processors, which operate at significantly lower supply voltages than mainstream microprocessors. Near-threshold or subthreshold SRAM designs are presented, which can open the door for revolutionary new applications such as wearable electronics, portable medical monitors, and implantable medical devices.

For emerging nonvolatile embedded memories, it is important to evaluate the impact they have on the architecture-level performance and on the total chip power consumption. The fifth article, "Modeling, Architecture, and Applications for Emerging Memory Technologies" by Yuan Xie at Pennsylvania State University, reviews recent advances in memory architecture design with the introduction of MRAM and PCRAM and discusses the benefits at various levels of memory hierarchy. Circuit and architecture techniques to overcome the limitations of emerging memory technologies, namely the long write delay and device wearout problems, are also presented.

In "Scalable Spin-Transfer Torque RAM Technology for Normally-Off Computing," Takayuki Kawahara from Hitachi presents recent trends of spin-transfer torque RAM technology and discusses its impact on the different layers of computer system hierarchy. A normally-off and instant-on operation enabled by nonvolatile memories can significantly reduce the power consumption of electronic systems without sacrificing performance. Several practical issues and possible solutions pertaining to future gigabit-scale STT-RAM systems are introduced.

The last article, "Fast-Write Resistive RAM (RRAM) for Embedded Applications" authored by Shyh-Shyuan Sheu et al., describes a new RRAM device with fast-write operation to improve the speed of embedded nonvolatile memories for microcontroller and mobile applications. A fully functional 1-Kbit RRAM macro has been demonstrated for the first time, utilizing an HfO 2-based insulator achieving a random access speed of 120 MHz.

Embedded memories have been and will continue to be one of the most, if not the most, important building blocks in a microprocessor system. Moore's law has led to significant scaling challenges and innovative solutions as well as new research directions for embedded memories. It is our sincere hope that this special issue will give readers an opportunity to learn about the most cutting-edge embedded-memory designs and provide a glimpse into the future of this exciting and dynamic area of research.


This special issue would not have been possible without the valuable contributions by many dedicated individuals. In particular, the guest editors would like to thank Design & Test editor-in-chief Krishnendu Chakrabarty for his encouragement and support, the editorial staff of the IEEE Computer Society for their exceptional work, Scott Davidson at Oracle for help with The Last Byte column, University of Minnesota's Sachin Sapatnekar for his advice on the special-issue topic, the reviewers for their expert comments, and the authors for the high-quality articles.

About the Authors

Chris H. Kim is an associate professor of electrical and computer engineering, University of Minnesota. His current research interests include digital, mixed-signal, and memory circuit design for silicon and nonsilicon technologies. He has a PhD in electrical and computer engineering from Purdue University. He is a senior member of IEEE.
Leland Chang is a manager at the IBM T.J. Watson Research Center. With a background in silicon CMOS scaling and high-speed embedded memory, his research currently focuses on power-efficient computing systems. He has a PhD in electrical engineering and computer sciences from the University of California, Berkeley. Contact him at
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