Issue No. 06 - November/December (2010 vol. 27)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2010.121
Tsu-Wei Tseng , National Central University
Jin-Fu Li , National Central University
Chih-Sheng Hou , National Central University
<p><it>Editor's note</it>:</p><p>Built-in-self-repair is an enabling approach for improving memory yield in system-on-chip designs. Reducing the overhead of repair circuits while minimizing the test and repair time is of prime importance. This article presents a fast parallel repair methodology for SoC memory cores and an associated automation framework.</p><p align="right">—<it>Swarup Bhunia, Case Western Reserve University</it></p>
design and test, SoC, embedded memories, built-in self-repair, redundancy analysis, yield improvement
J. Li, C. Hou and T. Tseng, "A Built-in Method to Repair SoC RAMs in Parallel," in IEEE Design & Test of Computers, vol. 27, no. , pp. 46-57, 2010.