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Issue No.05 - September/October (2010 vol.27)
pp: 50-59
Alodeep Sanyal , Synopsys
Syed M. Alam , Everspin Technologies
Sandip Kundu , University of Massachusetts at Amherst
<p>The continual scaling of device dimensions is increasing both parametric failures, stemming from circuit marginality issues, and soft errors, from the impact of high-energy particles on semiconductor surfaces. Effectively detecting and estimating such intermittent failures is crucial for reliability, availability, and serviceability (RAS) characterization of chips. This BIST-based approach distinguishes intermittent failures from permanent failures and reduces test time and cost.</p>
design and test, soft error, parametric failure, BIST, linear feedback shift register, multiple input signature register
Alodeep Sanyal, Syed M. Alam, Sandip Kundu, "BIST to Detect and Characterize Transient and Parametric Failures", IEEE Design & Test of Computers, vol.27, no. 5, pp. 50-59, September/October 2010, doi:10.1109/MDT.2010.30
1. V.D. Agrawal, C.R. Kime, and K.K. Saluja, "A Tutorial on Built-In Self-Test—Part I: Principles," IEEE Design and Test, vol. 10, no. 1, 1993, pp. 73-82.
2. A. Sanyal, S.M. Alam, and S. Kundu, "A Built-in Self-Test Scheme for Soft Error Rate Characterization," Proc. IEEE Int'l Online Testing Symp., IEEE Press, 2008, pp. 65-70.
3. M. Yilmaz et al., "Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier," Proc. Int'l Test Conf. (ITC 06), IEEE CS Press, 2006.
4. P.H. Bardell, W.H. McAnney, and J. Savir, Built-in Test for VLSI: Pseudorandom Techniques, John Wiley & Sons, 1987.
5. S. Das Gupta, R.G. Walther, and T.W. Williams, "An Enhancement to LSSD and Some Applications of LSSD in Reliability, Availability, and Serviceability," Proc. IEEE Int'l Fault Tolerance Computing Symp., 1981, IEEE Press, pp. 32-34.
6. K. Fukahori and P.R. Gray, "Computer Simulation of Integrated Circuits in the Presence of Electrothermal Interaction," IEEE J. Solid-State Circuits, vol. 11, no. 6, 1976, pp. 834-846.
7. A. Sanyal and S. Kundu, "A Built-In Test and Characterization Method for Circuit Marginality Related Failures," Proc. IEEE Int'l Symp. Quality Electronic Design, IEEE CS Press, 2008, pp. 838-843.
8. R. Madge et al., "In Search of the Optimum Test Set—Adaptive Test Methods for Maximum Defect Coverage and Lowest Test Cost," Proc. Int'l Test Conf. (ITC 04), IEEE CS Press, 2004, pp. 203-212.
9. G. Hetherington et al., "Logic BIST for Large Industrial Designs: Real Issues and Case Studies," Proc. Int'l Test Conf. (ITC 99), IEEE CS Press, 1999, pp. 358-367.
10. K.-J. Lee and K. Skadron, "Using Performance Counters for Runtime Temperature Sensing in High-Performance Processors," Proc. 19th IEEE Int'l Parallel and Distributed Processing Symp. (IPDPS 05), IEEE CS Press, 2005.
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