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Issue No. 05 - September/October (2010 vol. 27)
ISSN: 0740-7475
pp: 26-35
Fernando Gehm Moraes , Pontifícia Universidade Católica do Rio Grande do Sul
Ewerson Luiz de Souza Carvalho , Pontifícia Universidade Católica do Rio Grande do Sul
Ney Laert Vilar Calazans , Pontifícia Universidade Católica do Rio Grande do Sul
ABSTRACT
<p>Multiprocessor-system-on-a-chip (MPSoC) applications can consist of a varying number of simultaneous tasks and can change even after system design, enforcing a scenario that requires the use of dynamic task mapping. This article investigates dynamic task-mapping heuristics targeting reduction of network congestion in network-on-chip (NoC)-based MPSoCs. The proposed heuristics achieve up to 31% smaller channel load and up to 22% smaller packet latency than other heuristics.</p>
INDEX TERMS
design and test, dynamic task mapping, MPSoC, SoC, NoC
CITATION
Fernando Gehm Moraes, Ewerson Luiz de Souza Carvalho, Ney Laert Vilar Calazans, "Dynamic Task Mapping for MPSoCs", IEEE Design & Test of Computers, vol. 27, no. , pp. 26-35, September/October 2010, doi:10.1109/MDT.2010.106
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