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Issue No. 05 - September/October (2010 vol. 27)
ISSN: 0740-7475
pp: 6-13
Tetsushi Koide , Hiroshima University
Hans Mattausch , Hiroshima University
Norio Sadachika , Tsuneishi Shipbuilding
Shinya Izumi , Renesas Technology
Akihiro Kaya , Hiroshima University
Koh Johguchi , Hiroshima University
ABSTRACT
<p>As transistor size scales down, unavoidable process variations are rapidly increasing. Consequently, it's essential for designers to accurately estimate within-die and interdie variations so that circuits and integrated systems can operate correctly. This article describes an analysis of ring oscillators that were designed in 180-nm and 100-nm CMOS technologies, and discusses the oscillators' frequency variations as determined for different stage numbers and supply voltages.</p>
INDEX TERMS
design and test, within-wafer variation, within-die variation, CMOS, ring oscillators, compact model, surface potential, low power
CITATION
Tetsushi Koide, Hans Mattausch, Norio Sadachika, Shinya Izumi, Akihiro Kaya, Koh Johguchi, "Measurement-Based Ring Oscillator Variation Analysis", IEEE Design & Test of Computers, vol. 27, no. , pp. 6-13, September/October 2010, doi:10.1109/MDT.2010.57
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