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Issue No. 04 - July/August (2010 vol. 27)
ISSN: 0740-7475
pp: 70-71
Andrew B. Kahng , University of California, San Diego
ABSTRACT
<p>A key facet of "More than Moore" scaling comes under the heading of "3D"&#x2014;the stacking of multiple integrated-circuit dies using through-silicon vias (TSVs). Stacked-die products reached the marketplace decades ago, but with peripheral I/O on individual dies and interchip interconnect on the "side" of the stack. TSVs are a game changer, as this column explains.</p>
INDEX TERMS
design and test, interconnects, through-silicon vias, TSVs, scaling
CITATION
Andrew B. Kahng, "When is 3D 2B?", IEEE Design & Test of Computers, vol. 27, no. , pp. 70-71, July/August 2010, doi:10.1109/MDT.2010.92
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