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Issue No. 02 - March/April (2010 vol. 27)
ISSN: 0740-7475
pp: 51-67
Mohammad Tehranipoor , University of Connecticut, Storrs
Kenneth M. Butler , Texas Instruments
<p>As technology scales to 32 nm and functional frequency and density continue to rise, PSN effects, which can reduce a circuit's noise immunity and could lead to failures, pose new challenges to chip manufacturers and foundries. This article provides an overview of low-power and delay testing, and surveys ongoing research for analyzing and dealing with PSN effects during delay test and timing analysis.</p>
design and test, power supply noise (PSN), path delay testing, transition delay fault testing, timing analysis

M. Tehranipoor and K. M. Butler, "Power Supply Noise: A Survey on Effects and Research," in IEEE Design & Test of Computers, vol. 27, no. , pp. 51-67, 2010.
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