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Issue No. 02 - March/April (2010 vol. 27)
ISSN: 0740-7475
pp: 18-25
Xi-Wei Lin , Synopsys
Victor Moroz , Synopsys
ABSTRACT
<p><it>Editor's note:</it></p><p>Layout-dependent variations significantly affect device modeling, model extraction, and design solutions. A novel approach is proposed in this article to seamlessly integrate physical models of lithography, strained Si, and ion implantation processes, with layout geometry for efficient model generation.</p><p align="right"><it>&#x2014;Yu Cao, Arizona State University</it></p>
INDEX TERMS
CMOS, compact model, design and test, extraction, layout, lithography, mobility, proximity, stress, threshold voltage, variability
CITATION

V. Moroz and X. Lin, "Layout Proximity Effects and Modeling Alternatives for IC Designs," in IEEE Design & Test of Computers, vol. 27, no. , pp. 18-25, 2010.
doi:10.1109/MDT.2010.48
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