Issue No. 02 - March/April (2010 vol. 27)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2010.48
Xi-Wei Lin , Synopsys
Victor Moroz , Synopsys
<p><it>Editor's note:</it></p><p>Layout-dependent variations significantly affect device modeling, model extraction, and design solutions. A novel approach is proposed in this article to seamlessly integrate physical models of lithography, strained Si, and ion implantation processes, with layout geometry for efficient model generation.</p><p align="right"><it>—Yu Cao, Arizona State University</it></p>
CMOS, compact model, design and test, extraction, layout, lithography, mobility, proximity, stress, threshold voltage, variability
V. Moroz and X. Lin, "Layout Proximity Effects and Modeling Alternatives for IC Designs," in IEEE Design & Test of Computers, vol. 27, no. , pp. 18-25, 2010.