Issue No. 02 - March/April (2010 vol. 27)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2010.50
Samar K. Saha , University of Colorado at Colorado Springs
<p><it>Editor's note:</it></p><p>Process variability has become a critical issue in scaled CMOS design. This article provides a comprehensive view on the predominant variation sources in sub–90-nm devices, their impact on device and circuit performance, and various modeling approaches for statistical circuit analysis.</p><p align="right"><it>—Yu Cao, Arizona State University</it></p>
compact variability modeling, design and test, gate-oxide thickness variability, high-k dielectric, line-edge roughness, metal gate, polysilicon granularity, process variability, random discrete dopants, scaled CMOS technology, statistical compact modeling
S. K. Saha, "Modeling Process Variability in Scaled CMOS Technology," in IEEE Design & Test of Computers, vol. 27, no. , pp. 8-16, 2010.