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Issue No. 01 - January/February (2010 vol. 27)
ISSN: 0740-7475
pp: 92
Conference Reports
2009 IEEE European Test Symposium
Marcelo Lubaszewski, LATW general chair
Fabian Vargas, LATW program chair
The LATW 2009, held 2-5 March 2009, kicked off the technical program with a keynote speech by Kaushik Roy on design and test integration in the nanoscale era. The technical program also featured an invited talk by Hans-Joachim Wunderlich on the need for embedding diagnosis in reliable systems. Marie-Lise Flottes and Giorgio Di Natale presented a tutorial on ensuring testability without degrading security, and the tutorial by Vincent Pouget explained failure mechanisms in deep submicron technologies. Two TTEP tutorials were also presented. For more, visit
2009 IEEE DDECS Symposium
Zdenek Pliva, DDECS general chair
The 12th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems took place 15–17 April 2009 in Liberec, Czech Republic. This symposium, one of Central Europe's major scientific events, offers a forum for presenting results of research and practical applications of design, test, and diagnosis of microelectronic circuits and systems. Keynote speeches were given by Georges Gielen on an overview of problems due to increased variability and reliability; by Abhijit Chatterjee on results obtained in the design of cognitive computing and communication systems; and by Anton Chichkov on challenges for IC test. For more, visit
Shireesh Verma, Conexant Systems
This ITC panel was organized by Ramyanshu Datta of Texas Instruments and Stephen Sunter of Mentor Graphics, and moderated by Carl Moore of Maxim Integrated Products. Carl asked about the challenges EDA companies face in developing DFT automation for analog/mixed-signal functions, the key issues for DFT and BIST, the solutions needed most urgently, and how effectiveness could be measured. One of the presenters emphasized the need for defect-oriented tests correlated to performance tests, so that the latter could be eliminated. An attendee questioned whether DOT could be accepted since it would mean companies wouldn't directly test compliance with specifications. After the formal panel finished, a few panelists agreed to cooperate in proposing and developing an IEEE standard analog fault model. For a full report, visit
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