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Issue No. 01 - January/February (2010 vol. 27)
ISSN: 0740-7475
pp: 66-75
Akhilesh Tyagi , Iowa State University
Joseph Zambreno , Iowa State University
Alex Baumgarten , Microsoft
ABSTRACT
<p>Editor's note:</p><p>Hardware metering to prevent IC piracy is a challenging and important problem. The authors propose a combinational locking scheme based on intelligent placement of the barriers throughout the design in which the objective is to maximize the effectiveness of the barriers and to minimize the overhead.</p><p align="right"><it>&#x2014;Farinaz Koushanfar, Rice University</it></p>
INDEX TERMS
design and test, hardware metering, IC fabrication, IC piracy, IC security, reconfigurable-logic barriers, selection heuristics
CITATION
Akhilesh Tyagi, Joseph Zambreno, Alex Baumgarten, "Preventing IC Piracy Using Reconfigurable Logic Barriers", IEEE Design & Test of Computers, vol. 27, no. , pp. 66-75, January/February 2010, doi:10.1109/MDT.2010.24
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