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Issue No.01 - January/February (2010 vol.27)
pp: 66-75
Alex Baumgarten , Microsoft
Akhilesh Tyagi , Iowa State University
Joseph Zambreno , Iowa State University
<p>Editor's note:</p><p>Hardware metering to prevent IC piracy is a challenging and important problem. The authors propose a combinational locking scheme based on intelligent placement of the barriers throughout the design in which the objective is to maximize the effectiveness of the barriers and to minimize the overhead.</p><p align="right"><it>&#x2014;Farinaz Koushanfar, Rice University</it></p>
design and test, hardware metering, IC fabrication, IC piracy, IC security, reconfigurable-logic barriers, selection heuristics
Alex Baumgarten, Akhilesh Tyagi, Joseph Zambreno, "Preventing IC Piracy Using Reconfigurable Logic Barriers", IEEE Design & Test of Computers, vol.27, no. 1, pp. 66-75, January/February 2010, doi:10.1109/MDT.2010.24
1. "Intellectual Property (IP) Challenges and Concerns of the Semiconductor Equipment and Materials Industry," white paper, Semiconductor Equipment and Materials Int'l, Apr. 2008; ssLINKP043701.
2. J. Huang and J. Lach, "IC Activation and User Authentication for Security-Sensitive Systems," Proc. Int'l Workshop Hardware-Oriented Security and Trust (HOST 08), IEEE CS Press, 2008, pp. 76-80.
3. J. Roy, F. Koushanfar, and I. Markov, "EPIC: Ending Piracy of Integrated Circuits," Proc. Design, Automation and Test in Europe Conf. (DATE 08), ACM Press, 2008, pp. 1069-1074.
4. S. Kumar et al., "The Butterfly PUF Protecting IP on Every FPGA," Proc. Int'l Workshop Hardware-Oriented Security and Trust (HOST 08), IEEE CS Press, 2008, pp. 67-70.
5. J. Lee et al., "A Technique to Build a Secret Key in Integrated Circuits for Identification and Authentication Applications," Proc. Symp. VLSI Circuits, IEEE Press, 2004, pp. 176-179.
6. K. Lofstrom, R. Daasch, and D. Taylor, "IC Identification Circuit Using Device Mismatch," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 00), IEEE Press, 2000, pp. 372-373.
7. Y. Su, J. Holleman, and B. Otis, "A 1.6pJ/bit 96% Stable Chip ID Generating Circuit Using Process Variations," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 07), IEEE Press, 2007, pp. 406-407, 611.
8. G.E. Suh and S. Devadas, "Physical Unclonable Functions for Device Authentication and Secret Key Generation," Proc. 44th Design Automation Conf. (DAC 07), ACM Press, pp. 9-14.
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