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With increasing marginalities in the nanometer technology regime, design considerations for yield and reliability of operation have become critical for digital, analog, and mixed-signal circuits. Die-to-die and within-die parameter variations have emerged as major concerns. The impact of manufacturing variability is accentuated by low-power design techniques such as voltage scaling, gate sizing, or dual- VTH assignment. Temporal variations in device parameters due to environmental effects such as temperature or voltage fluctuations or device aging effects such as bias temperature instability, hot carrier injection, and time-dependent dielectric breakdown add to the reliability concern imposed by process variations. Post-silicon calibration and repair strategies constitute a promising class of solutions to address variation and power induced yield and reliability concerns. Such techniques can be applied both during manufacturing test for yield improvement and at runtime for dynamic adaptation to temporal parameter variations.

IEEE Design & Test seeks original manuscripts on post-silicon calibration and repair techniques in digital, analog, and mixed-signal ICs encompassing both design and test aspects, scheduled for publication in November/December 2010. Topics of interest include (but are not limited to):

  • Process monitor for die characterization
  • Self-calibration and self-repair for logic, memory and analog cores, and mixed-signal and DSP systems
  • Calibration and compensation of within-die parameter variations
  • Yield and test cost improvement using post-silicon calibration and repair
  • Aging characterization and dynamic adaptation to aging/temperature

Submission and review procedures

Prospective authors should follow the submission guidelines for IEEE Design & Test. All manuscripts must be submitted electronically to the IEEE Manuscript Central Web site at Indicate that you are submitting your article to the special issue on "Post-Silicon Calibration and Repair for Yield and Reliability Improvement." All articles will undergo the standard IEEE Design & Test review process. Submitted manuscripts must not have been previously published or currently submitted for publication elsewhere. Manuscripts must not exceed 5,000 words, including figures (with each average-size figure counting as 200 words) and a maximum of 12 References (30 for surveys). This amounts to about 4,000 words of text and a maximum of five small to medium figures. Accepted articles will be edited for clarity, structure, conciseness, grammar, passive to active voice, logical organization, readability, and adherence to style. Please see IEEE D&T Author Resources at, then scroll down and click on Author Center for submission guidelines and requirements.


  • Articles due for review: 8 March 2010
  • Reviews completed: 5 May 2010
  • Article revisions due: 17 June 2010
  • Notice of final acceptance: 14 July 2010
  • All materials due for edit: 20 August 2010


Please direct questions regarding this special issue to Guest Editors Swarup Bhunia ( and Rahul Rao (

Special Issue on Post-Silicon Calibration and Repair for Yield and Reliability Improvement

November/December 2010

Guest Editors: Swarup Bhunia (Case Western Reserve University) and Rahul Rao (IBM T.J. Watson Research Center)

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