Issue No. 06 - November/December (2009 vol. 26)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2009.149
Yu Cao , Arizona State University
Jim Tschanz , Intel
Pradip Bose , IBM Thomas J. Watson Research Center
<p><scp>VLSI</scp> design is driven by an ever-increasing challenge to cope with unreliable components at the device, circuit, and system levels. Reliability challenges include, for example, bias-temperature instability (BTI), dielectric breakdown, early-life failure, and soft errors, as well as their interaction with statistical process variation. The impact of unreliability must be managed at various levels of the design abstraction. This special issue addresses the problem of design for reliability at the 32-nm node and beyond, in the context of the emerging threat of progressively unreliable components used in VLSI chip design.</p>
32-nm node, CMOS, design and test, reliability, soft errors, VLSI chip design
Y. Cao, J. Tschanz and P. Bose, "Guest Editors' Introduction: Reliability Challenges in Nano-CMOS Design," in IEEE Design & Test of Computers, vol. 26, no. , pp. 6-7, 2009.