Issue No. 05 - September/October (2009 vol. 26)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2009.127
David S. Kung , IBM T.J. Watson Research Center
<p>The impending doom of CMOS scaling has semiconductor mavericks scrambling for alternative solutions to continue increasing the device density per chip. One serious candidate is 3D integration in which the planar manufacturing technology extends skyward into the third dimension, much like skyscrapers. Similarities between chip architecture and building architecture are plentiful, and the author draws some parallels between the two.</p>
3D IC, design and test, stacking, CMOS scaling
D. S. Kung, "The fate of stacking," in IEEE Design & Test of Computers, vol. 26, no. , pp. 112, 2009.