First ACM/IEEE A. Richard Newton Technical Impact Award in electronic design automation
The first recipients of the ACM/IEEE A. Richard Newton Technical Impact Award in EDA for outstanding technical contributions are Robert K. Brayton, Richard Rudell, Alberto Sangiovanni-Vincentelli, and Albert R. Wang for their seminal paper, "MIS: A Multiple-Level Logic Optimization System." The award was presented during DAC's opening session 28 July in San Francisco.
The ACM Special Interest Group on Design Automation (SigDA) and the IEEE CEDA created the yearly award last year to honor the late Richard Newton, dean of engineering at the University of California, Berkeley. The award acknowledges an individual or individuals for outstanding technical contributions to EDA recognized over a significant period of time. The selection criteria are based on a high-impact, seminal paper published at least 10 years ago by either the ACM or the IEEE.
Published in the IEEE Transactions on CAD in November 1987, the "MIS: A Multiple-Level Logic Optimization System" paper established the groundwork of modern multilevel logic synthesis and has triggered follow-up research over the past 20 years. Sharad Malik, professor at Princeton University, notes: "The MIS paper is a fundamental paper in EDA, to be counted in the group with the original SPICE, Espresso, and Binary Decision Diagram papers. The ideas presented in this publication have served as the foundation for the field of logic synthesis, in research as well as industrial practice."
The paper by Brayton, Rudell, Sangiovanni-Vincentelli, and Wang has made major contributions to three domains. The first is research. It established the basic principles of a script-based multilevel logic synthesis flow and described several algorithmic ingredients to such a flow. The MIS tool implemented these results in an open source package and was broadly adapted by research groups in academia and industry as a research and benchmarking platform for logic optimization. In the second domain, education, the MIS software was used for graduate research in logic synthesis. MIS and its follow-up implementations enabled at least 50 PhD and many master's thesis projects leading to a large body of results over 10 years.
Finally, the MIS paper contributed to industrial practice because this software was critical in the rapid industrial adoption of logic synthesis. It was used internally in companies such as Intel and adapted by multiple startup companies as the foundation of their products.
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Results from 2008 Journal Citations Report
Thomson Reuters has recently published the 2008 editions of the Journal Citations Reports. All Council-related publications sponsored by the IEEE Circuits and Systems Society experienced a significant improvement of their impact factor (IF). More specifically:
1. IEEE Transactions on Circuits and Systems for Video Technology. 2008 IF = 2.951 with an increase of 75% with respect to 2007.
2. IEEE Transactions on Circuits and Systems— Part I: Regular papers. 2008 IF = 2.043 with an increase of 70% with respect to 2007.
3. IEEE Transactions on Circuits and Systems— Part II: Express briefs. 2008 IF = 1,436 with an increase of 30% with respect to 2007.
4. IEEE Transactions on Computer Aided Design. 2008 IF = 1.466 with an increase of 88% with respect to 2007.
IF is a measure of the impact of content published in a journal as evidenced by references to its content on a rolling two-year basis. IF is computed as the average number of citations in a year given to those papers in a journal that were published during the two preceding years. This effectively highlights the tremendous effort made by the editors in chief and editorial boards of the CASS transactions to improve timeliness of the review process and technical quality of the published manuscripts. With improved IF rankings, we can all look forward to more high-quality content in council publications.
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Memocode Conference and codesign contest
The seventh annual Memocode Conference, and the third codesign contest, were held this summer. Memocode draws its participation from the community of researchers interested in formal techniques applied to system-level design and analysis. This sets it apart from both the embedded systems design and tools community that primarily uses ad hoc hardware and software tools, and the formal technology community chiefly concerned with verification problems.
Programmatically, the single-track conference featured 17 paper presentations, 3 posters, and invited talks by Amir Pnueli (NYU), David Harel (Weizmann Institute), and Martin Rinard (MIT). Of special interest was a tutorial on embedded system security, attacks, and countermeasures, by Thomas Popp (Graz University of Technology). There was a lively panel discussing the state of hardware description languages (especially in view of the relative maturity of software languages). One session presented the results of the third annual codesign contest where winners of the two awards described their methodology and techniques they employed. Partially sponsored by CEDA, the conference and contest are also sponsored by Bluespec, IBM Research, and Xilinx as well as ACM SIGBED, SIGDA, and the IEEE CAS societies.
The conference was held this year at the MIT Stata Center and drew 45 attendees, about 40% of whom came from abroad. Memocode venues historically have alternated between the US and Europe in successive years; consequently, the 2010 conference will likely be in Europe.
As in previous years, the codesign contest followed an open format with few restrictions on who can participate and what methodologies and platforms can be used. The entries must be physically demonstrable and completed within one month. Prizes are awarded for both the highest absolute performance regardless of platform and the highest performance when normalized by the platform's capability.
The contest is intended to promote three major goals. First, the contest aims to foster greater interest in hands-on hardware and software codesign activities in both academic and industrial settings. Second, the contest provides an open, unbiased forum where academic and industry tool developers can showcase the advantages and issues in their design methodologies or platforms. Third, the design challenge and the wide variety of solutions collected over the years (most of which are available in open-source forms on the contest website) serve as openly available best-effort benchmarks.
Each design submission is evaluated for both absolute and normalized performance. The absolute performance metric is the geometric average speedup over a prescribed set of test inputs relative to a provided reference implementation. For the normalized performance competition, the speedup is normalized by the platform's capability to level the playing field between platforms and to reward a design's efficiency. In addition, a subjective evaluation of design elegance as determined by a panel of judges. This year, the two organizers were joined by Kees Vissers (Xilinx) on the panel.
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The inaugural issue of the IEEE Embedded Systems Letter is ready with seven outstanding papers, selected from among the broad initial submission. The list of these papers follows:
• "Temperature-Driven Time Synchronization"
• "Verification of Synchronous Elastic Processors"
• "ASIP-Based Universal Demapper for Multi Wireless Standards"
• "Portability versus Efficiency Trade-offs in MAC Implementations for Microsensor Platforms"
• "BOUNCE, A New High-Resolution Time Interval Measurement Architecture"
• "Optimizing Bandwidth of Call Traces for Wireless Embedded Systems"
• "Hardware Resource Virtualization for Dynamically Partially Reconfigurable Systems"
Please contact José L. Ayala (firstname.lastname@example.org) for more information.
CEDA conferences provide excellent opportunities for those interested in learning about the latest technical trends in electronic design and automation. If you'd like to participate or you have an idea about new topics of interest for our conferences, please contact William Joyner (email@example.com), CEDA vice president of conferences.
19th International Workshop on Power and Timing Modeling, Optimization, and Simulation (PATMOS)
9–11 September 2009
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)
11–16 October 2009
4th International Conference on Nano Networks (Nano-Net)
18–20 October 2009
IEEE/ACM 2009 International Conference on Computer-Aided Design (ICCAD)
2–5 November 2009
San Jose, California
Formal Methods in Computer-Aided Design Conference (FMCAD)
15–18 November 2009
IEEE Embedded Systems Lettersis open for submissions. Visit: mc.manuscriptcentral.com/les-ieee