Issue No. 05 - September/October (2009 vol. 26)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2009.121
Hao Yu , Berkeley Design Automation
Lei He , University of California, Los Angeles
Mau-Chung Frank Chang , University of California, Los Angeles
<p>Existing shield insertion for multiple signal nets can lead to a nonuniformly distributed, capacitive-coupling length and inductive return paths, introducing large delays and delay variation by crosstalk. This article discusses a twisted, staggered interconnect structure that reduces both inductive and capacitive crosstalk. The proposed design reduces delay by 25% and reduces delay variation by 25× compared to designs employing coplanar shields.</p>
on-chip signaling, crosstalk reduction, shield insertion, interconnect structure, chip multiprocessors
L. He, M. Frank Chang and H. Yu, "Robust On-Chip Signaling by Staggered and Twisted Bundle," in IEEE Design & Test of Computers, vol. 26, no. , pp. 92-104, 2009.