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Issue No. 05 - September/October (2009 vol. 26)
ISSN: 0740-7475
pp: 74-82
Jayashree Saxena , Texas Instruments
John M. Carulli Jr. , Texas Instruments
Amit Nahar , Texas Instruments
W. Robert Daasch , Portland State University
Kenneth M. Butler , Texas Instruments
ABSTRACT
<p>Editor's note:</p><p>Today's SoC designs contain many types of circuitry, each with various test types. This article revisits the classic test escape models and highlights their limitations in a test environment with different types of circuits and different test types with overlapping coverage. A new methodology for test escape rate prediction is presented.</p><p align="right"><it>&#x2014;Nur A. Touba, University of Texas</it></p>
INDEX TERMS
Defect level, defective parts per million (DPPM), design and test, test escapes, yield, fault coverage
CITATION
Jayashree Saxena, John M. Carulli Jr., Amit Nahar, W. Robert Daasch, Kenneth M. Butler, "Multidimensional Test Escape Rate Modeling", IEEE Design & Test of Computers, vol. 26, no. , pp. 74-82, September/October 2009, doi:10.1109/MDT.2009.118
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