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Issue No. 05 - September/October (2009 vol. 26)
ISSN: 0740-7475
pp: 26-35
Krishnendu Chakrabarty , Duke University
Hsien-Hsin S. Lee , Georgia Institute of Technology
ABSTRACT
<p>Editor's note:</p><p>One of the challenges for 3D technology adoption is the insufficient understanding of 3D testing issues and the lack of DFT solutions. This article describes testing challenges for 3D ICs, including problems that are unique to 3D integration, and summarizes early research results in this area.</p><p align="right"><it>&#x2014;Yuan Xie, Pennsylvania State University</it></p>
INDEX TERMS
3D ICs, 3D integration, interconnect scaling, defects, CMOS, DFT, design and test
CITATION
Krishnendu Chakrabarty, Hsien-Hsin S. Lee, "Test Challenges for 3D Integrated Circuits", IEEE Design & Test of Computers, vol. 26, no. , pp. 26-35, September/October 2009, doi:10.1109/MDT.2009.125
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