Issue No. 05 - September/October (2009 vol. 26)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2009.125
Hsien-Hsin S. Lee , Georgia Institute of Technology
Krishnendu Chakrabarty , Duke University
<p>Editor's note:</p><p>One of the challenges for 3D technology adoption is the insufficient understanding of 3D testing issues and the lack of DFT solutions. This article describes testing challenges for 3D ICs, including problems that are unique to 3D integration, and summarizes early research results in this area.</p><p align="right"><it>—Yuan Xie, Pennsylvania State University</it></p>
3D ICs, 3D integration, interconnect scaling, defects, CMOS, DFT, design and test
K. Chakrabarty and H. S. Lee, "Test Challenges for 3D Integrated Circuits," in IEEE Design & Test of Computers, vol. 26, no. , pp. 26-35, 2009.