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Issue No. 05 - September/October (2009 vol. 26)
ISSN: 0740-7475
pp: 15-25
Sachin S. Sapatnekar , University of Minnesota, Twin Cities
Pingqiang Zhou , University of Minnesota, Twin Cities
Karthikk Sridharan , University of Minnesota, Twin Cities
ABSTRACT
<p>Editor's note:</p><p>This article studies one of the EDA problems for 3D IC design. The article presents a design automation solution for power grid optimization in 3D ICs. The authors propose a congestion-aware 3D power supply network optimization algorithm, which applies a sequence-of-linear-programs&#x2013;based method to optimize the power grid design.</p><p align="right"><it>&#x2014;Yuan Xie, Pennsylvania State University</it></p>
INDEX TERMS
decoupling capacitors, design and test, MIM decap, CMOS decap, power grid, 3D integration
CITATION
Sachin S. Sapatnekar, Pingqiang Zhou, Karthikk Sridharan, "Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity", IEEE Design & Test of Computers, vol. 26, no. , pp. 15-25, September/October 2009, doi:10.1109/MDT.2009.120
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