Issue No. 05 - September/October (2009 vol. 26)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2009.120
Pingqiang Zhou , University of Minnesota, Twin Cities
Karthikk Sridharan , University of Minnesota, Twin Cities
Sachin S. Sapatnekar , University of Minnesota, Twin Cities
<p>Editor's note:</p><p>This article studies one of the EDA problems for 3D IC design. The article presents a design automation solution for power grid optimization in 3D ICs. The authors propose a congestion-aware 3D power supply network optimization algorithm, which applies a sequence-of-linear-programs–based method to optimize the power grid design.</p><p align="right"><it>—Yuan Xie, Pennsylvania State University</it></p>
decoupling capacitors, design and test, MIM decap, CMOS decap, power grid, 3D integration
S. S. Sapatnekar, P. Zhou and K. Sridharan, "Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity," in IEEE Design & Test of Computers, vol. 26, no. , pp. 15-25, 2009.