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Issue No. 04 - July/August (2009 vol. 26)
ISSN: 0740-7475
pp: 88-95
Anmol Mathur , Calypto Design Systems
Masahiro Fujita , University of Tokyo
Edmund Clarke , Carnegie Mellon University
Pascal Urard , STMicroelectronics
<p>Editor's note:</p><p>High-level synthesis facilitates the use of formal verification methodologies that check the equivalence of the generated RTL model against the original source specification. The article provides an overview of sequential equivalence checking techniques, its challenges, and successes in real-world designs.</p><p align="right">&#x2014;Andres Takach, Mentor Graphics</p>
system-level model, sequential equivalence, functional equivalence, design and test, formal analysis, correctness

A. Mathur, E. Clarke, M. Fujita and P. Urard, "Functional Equivalence Verification Tools in High-Level Synthesis Flows," in IEEE Design & Test of Computers, vol. 26, no. , pp. 88-95, 2009.
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