Issue No. 04 - July/August (2009 vol. 26)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2009.85
Yuan Xie , Pennsylvania State University
Yibo Chen , Pennsylvania State University
<p>Editor's note:</p><p>CMOS process variability is a major challenge in deep-submicron SoC designs. The variations in transistor parameters are complicating both timing and power consumption prediction. This article surveys recent progress in the statistical high-level synthesis area.</p><p>—Philippe Coussy, Université de Bretagne-Sud</p>
statistical high-level synthesis, design and test, process variation, parametric yield
Y. Chen and Y. Xie, "Statistical High-Level Synthesis under Process Variability," in IEEE Design & Test of Computers, vol. 26, no. , pp. 78-87, 2009.