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Issue No. 04 - July/August (2009 vol. 26)
ISSN: 0740-7475
pp: 58-67
Chad Spackman , CebaTech
Sandeep K. Shukla , Virginia Polytechnic and State University
Sumit Ahuja , Virginia Polytechnic and State University
ABSTRACT
<p>Editor's note:</p><p>This article shows how design space exploration can be realized through high-level synthesis. It presents a case study of a hardware implementation of the Advanced Encryption Standard (AES) Rijndael algorithm. Starting from the algorithmic specification, the authors generate various architectures by using the C2R compiler.</p><p align="right">&#x2014;Philippe Coussy, Universit&#x00E9; de Bretagne-Sud</p>
INDEX TERMS
high-level synthesis, design and test, ESL, ASIC, FPGA, ANSI C, Verilog, verification, power reduction, C2R methodology
CITATION
Swathi T. Gurumani, Chad Spackman, Sandeep K. Shukla, Sumit Ahuja, "Hardware Coprocessor Synthesis from an ANSI C Specification", IEEE Design & Test of Computers, vol. 26, no. , pp. 58-67, July/August 2009, doi:10.1109/MDT.2009.81
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