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Issue No.04 - July/August (2009 vol.26)
pp: 46-57
Maciej Ciesielski , University of Massachusetts, Amherst
Jeremie Guillot , Lab-STICC, Université de Bretagne Sud, Lorient, France
Daniel Gomez-Prado , University of Massachusetts, Amherst
Emmanuel Boutillon , Lab-STICC, Université de Bretagne Sud, Lorient, France
<p>Editor's note:</p><p>This article provides an overview of a canonical representation for arithmetic expressions and how it can be used to obtain various factorizations of such expressions to optimize them. The applicability of the approach is demonstrated in a high-level synthesis flow.</p><p align="right">&#x2014;Andres Takach, Mentor Graphics</p>
high-level synthesis, design and test, dataflow graphs, symbolic algebra, Taylor expansion diagrams
Maciej Ciesielski, Jeremie Guillot, Daniel Gomez-Prado, Emmanuel Boutillon, "High-Level Dataflow Transformations Using Taylor Expansion Diagrams", IEEE Design & Test of Computers, vol.26, no. 4, pp. 46-57, July/August 2009, doi:10.1109/MDT.2009.82
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5. D. Gomez-Prado et al., "Optimizing Dataflow Graphs to Minimize Hardware Implementations," Proc. Design Automation and Test in Europe (DATE 09), IEEE CS Press, 2009, pp. 117-122.
6. M. Ciesielski et al., "Data-Flow Transformations Using Taylor Expansion Diagrams," Proc. Design Automation and Test in Europe (DATE 07), IEEE CS Press, 2007, pp. 455-460.
7. J. Guillot, "Optimization Techniques for High Level Synthesis and Pre-Compilation Based on Taylor Expansion Diagrams," doctoral dissertation, Lab-STICC, UniversitéBretagne Sud, 2008.
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