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Issue No. 04 - July/August (2009 vol. 26)
ISSN: 0740-7475
pp: 34-45
Soujanna Sarkar , Texas Instruments
Shashank Dabral , Texas Instruments
Praveen K. Tiwari , Interra Systems
Raj S. Mitra , Texas Instruments
<p>Editor's note:</p><p>This article is a designer's perspective on the benefits and challenges of using commercially available HLS tools. The authors have used three such tools for synthesizing industrial ASICs. They discuss their impact on four criteria: design goals, verification closure, ECO handling, and productivity gains.</p><p align="right">&#x2014;Philippe Coussy, Universit&#x00E9; de Bretagne Sud</p>
high-level synthesis, design and test, ESL design, ASIC

R. S. Mitra, S. Dabral, P. K. Tiwari and S. Sarkar, "Lessons and Experiences with High-Level Synthesis," in IEEE Design & Test of Computers, vol. 26, no. , pp. 34-45, 2009.
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