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It is widely recognized that process variation is emerging as a fundamental challenge to IC design with scaled CMOS technology. It is also recognized that the variation will have profound impact on nearly all aspects of circuit performance. While some of the negative effects of variability can be handled with improvements in the manufacturing process, the industry is starting to accept the fact that some of the effects are better mitigated during the design process. Handling variability in the design process will require accurate and consistent models of variability and its dependence on designable parameters, and its spatial and temporal distribution. Such models are quite different from the "corner" models deployed thus far to model manufacturing variability. As a consequence, the compact modeling of systematic, spatial, and random variations is essential to abstract the physical level variations into a format the designers can utilize.

IEEE Design and Test seeks original manuscripts for a special issue on Compact Variability Modeling for Nanometer CMOS Technology, scheduled for publication in March/April 2010. This special issue will provide the audience of this magazine a comprehensive overview on the challenges of compact variability modeling and the current practice, as well as future research directions. Topics of interest include (but not limited to):

  • Physics mechanisms and technology trends of device-level variations
  • First-principles simulation methods for predicting variability
  • Compact modeling of variations in devices and interconnect
  • Novel implementation and simulation techniques for dealing with variability
  • Variability bounding, characterization, and extraction
  • Device and circuit level modeling techniques

Submission and review procedures

Prospective authors should follow the submission guidelines for IEEE Design & Test. All manuscripts must be submitted electronically to the IEEE Manuscript Central Web site at Indicate that you are submitting your article to the special issue on "Compact Variability Modeling." All articles will undergo the standard IEEE Design & Test review process. Submitted manuscripts must not have been previously published or currently submitted for publication elsewhere. Manuscripts must not exceed 5,000 words, including figures (with each average-size figure counting as 150 words) and including a maximum of 12 References (50 for surveys). This amounts to about 4,200 words of text and a maximum of five small to medium figures. Accepted articles will be edited for clarity, structure, conciseness, grammar, passive to active voice, logical organization, readability, and adherence to style. Please see the IEEE D&T Author Resources at, then scroll down and click on Author Center for submission guidelines and requirements.


  • Submissions deadline: 15 September 2009
  • Reviews completed: 20 October 2009
  • Revisions (if required) due: 15 November 2009
  • Notification of final acceptance: 15 December 2009
  • Submission of final version: 1 January 2010


Please direct questions regarding this special issue to Guest Editors Frank Liu ( and Yu Cao (

Special Issue on Compact Variability Modeling for Nanometer CMOS Technology

Guest Editors: Frank Liu (IBM Austin Research Lab)

Yu Cao (Arizona State University)

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