Issue No. 04 - July/August (2009 vol. 26)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2009.72
<p>To manage design complexity and cost, the next-generation design methodology must enable the highest possible level of abstraction; hide, insofar as possible, implementation details from designers; allow efficient design reuse, including the reuse of IP blocks, underlying architectures, and a large portion of embedded software across multiple generations; and provide flexibility in the system architecture of computation, communications, and storage elements. High-level synthesis is necessary and critical in such a solution. Consequently, this issue of <it>IEEE Design & Test</it> presents nine articles to review the progress of high-level synthesis research and which examine various aspects of this up-and-coming methodology.</p>
design and test, high-level synthesis, design complexity
"From the EIC: Building and verifying hardware at a higher level of abstraction," in IEEE Design & Test of Computers, vol. 26, no. , pp. 2, 2009.