Issue No. 03 - May/June (2009 vol. 26)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2009.53
Ishwar Parulkar , Sun Microsystems
Babu Turumella , Sun Microsystems
<p>This article describes a comprehensive approach for silicon debug of a server chipset that includes a high-performance, third-generation chip-multithreaded (CMT) Sparc microprocessor. Efficiently debugging the chipset required a combination of debug features in silicon and system platforms, firmware support for debug, test generation tools, and debug data interpretation tools. Several useful lessons were learned in the process.</p>
verification, test generation, design and test, multithreaded processors, server chipset, debug, SerDes, CMT Sparc microprocessor, RAS
B. Turumella and I. Parulkar, "Comprehensive Approach to High-Performance Server Chipset Debug," in IEEE Design & Test of Computers, vol. 26, no. , pp. 70-77, 2009.