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The emergence of a globalized, horizontal semiconductor business model raises a set of concerns involving the security and trust of the information systems on which modern society is increasingly reliant for mission-critical functionality. Hardware security and trust issues span a broad range including threats related to the malicious insertion of Trojan circuits designed, for example, to act as a silicon time bomb to disable a chip, to intellectual property (IP) and integrated circuit (IC) piracy, to untrusted third-party IP blocks, to attacks designed to extract encryption keys and IP from a chip, and to malicious system disruption and diversion. Trojans can be inserted into a circuit or system developed by a third-party IP vendor, system integrator, or foundry.

IEEE Design and Test seeks original manuscripts for a special issue on Verifying Physical Trustworthiness of Integrated Circuits and Systems scheduled for publication in January/February 2010. Topics of interest include (but are not limited to) the following:

  • Trojan detection and isolation
  • Authenticating foundry of origin
  • Watermarking
  • IC metering
  • Physical unclonable functions (PUFs)
  • Hardware intrusion detection and prevention
  • Scan-chain encryption

Submission and review procedures

Prospective authors should follow the submission guidelines for IEEE Design & Test. All manuscripts must be submitted electronically to the IEEE Manuscript Central Web site at Indicate that you are submitting your article to the special issue on "Verifying Physical Trustworthiness of Integrated Circuits and Systems." All articles will undergo the standard IEEE Design & Test review process. Submitted manuscripts must not have been previously published or currently submitted for publication elsewhere. Manuscripts must not exceed 5,000 words, including figures (with each average-size figure counting as 150 words) and including a maximum of 12 References (50 for surveys). This amounts to about 4,200 words of text and a maximum of five small to medium figures. Accepted articles will be edited for clarity, structure, conciseness, grammar, passive to active voice, logical organization, readability, and adherence to style. Please see the IEEE D&T Author Resources at, then scroll down and click on Author Center for submission guidelines and requirements.


  • Submissions deadline: 1 August 2009
  • Reviews completed: 7 September 2009
  • Revisions (if required) due: 28 September 2009
  • Notification of final acceptance: 28 October 2009
  • Submission of final version: 10 November 2009


Please direct questions regarding this special issue to Guest Editors Mohammad Tehranipoor ( and Farinaz Koushanfar (

Special Issue on Verifying Physical Trustworthiness of Integrated Circuits and Systems

Guest Editors: Mohammad Tehranipoor (University of Connecticut)

Farinaz Koushanfar (Rice University)

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