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Guest Editors' Introduction: The Status of IEEE Std 1500—Part 2

Erik Jan Marinissen, IMEC
Yervant Zorian, Virage Logic

Pages: pp. 4

You are looking at Part 2 of the IEEE Design & Test special issue on the status of IEEE Std 1500. The first issue, published in January/February 2009, could contain only a maximum of six articles, which was insufficient space to publish all the good articles that we had received and that had survived Design & Test's rigorous review procedure. Hence, in front of you is Part 2, containing another three articles. And, unlike the quality of many sequels that Hollywood produces in response to the success of its products, the contents of this Part 2 are at least as good as what we published in Part 1!

The first article, "Automating IEEE 1500 Core Test—An EDA Perspective" by Krishna Chakravadhanula and Vivek Chickermane, describes an automated test synthesis methodology and tool suite that combines support for IEEE-1500-wrapped cores and test data compression hardware in a production environment. The article presents experimental results for various cores. Two other EDA perspectives on IEEE 1500 can be found in Part 1 of our special issue on IEEE 1500.

In "Are IEEE-1500-Compliant Cores Really Compliant to the Standard?," Alfredo Benso et al. address the issue of compliance verification. They present a verification component that can be added to an overall SoC verification framework, based on a commercial verification tool suite. For another IEEE-1500 verification article, refer to Part 1 of this special issue.

The last article is "Test Data Volume Comparison: Monolithic vs. Modular SoC Testing" by Ozgur Sinanoglu et al. The authors show, through theoretic analysis as well as with experimental data on industrial SoCs, that the modular SoC testing enabled by IEEE 1500 reduces overall test data volume significantly when compared to monolithic testing. This benefit is due to the fact that modular testing allows each core to be tested with only those test patterns it specifically requires, instead of a global maximum determined by the hardest-to-test core.

With these three articles, we conclude our double special issue. We hope that Part 2 will earn just as good a reception as was the case for Part 1.

About the Authors

Erik Jan Marinissen is a principal scientist at IMEC and a member of the editorial board of IEEE Design & Test. His research interests include all aspects of VLSI test and DFT. He has a PDEng in computing science from Eindhoven University of Technology. He is a senior member of the IEEE, and he has served as EIC of the IEEE 1500 standardization working group for embedded-core test.
Yervant Zorian is vice president and chief scientist at Virage Logic, and he is an EIC Emeritus of IEEE Design & Test. He has a PhD in electrical engineering from McGill University. He is a Fellow of the IEEE, and he founded and chairs the IEEE 1500 standardization working group for embedded-core test.
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