Issue No. 02 - March/April (2009 vol. 26)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2009.37
Li-Ming Denq , National Tsing Hua University
Yu-Tsao Hsing , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
<p>Many embedded memories in SoCs have wide data words, leading to a high routing penalty in the BIST circuits. This novel hybrid BIST architecture reduces this routing penalty, while allowing at-speed test and diagnosis of memory cores. The MECA system facilitates mapping the diagnostic syndrome to the memory cell's defect information. A failure bitmap viewer provides visual information for design and process diagnostics.</p>
routing penalty, at-speed testing, hybrid BIST, diagnostic syndrome, failure bitmap, yield enhancement, MECA system, routing-area overhead
Y. Hsing, C. Wu and L. Denq, "Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories," in IEEE Design & Test of Computers, vol. 26, no. , pp. 64-73, 2009.