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Issue No. 02 - March/April (2009 vol. 26)
ISSN: 0740-7475
pp: 44-51
Wei Zhang , Southern Illinois University Carbondale
ABSTRACT
<p>Using a cache vulnerability factor to measure the susceptibility of cache memories to transient errors at the architecture level can help designers make appropriate cost and reliability trade-offs at early design cycles. Two early write-back strategies can also improve the reliability of write-back data caches without compromising performance.</p>
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CITATION
Wei Zhang, "Computing and Minimizing Cache Vulnerability to Transient Errors", IEEE Design & Test of Computers, vol. 26, no. , pp. 44-51, March/April 2009, doi:10.1109/MDT.2009.29
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