Issue No. 02 - March/April (2009 vol. 26)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2009.29
Wei Zhang , Southern Illinois University Carbondale
<p>Using a cache vulnerability factor to measure the susceptibility of cache memories to transient errors at the architecture level can help designers make appropriate cost and reliability trade-offs at early design cycles. Two early write-back strategies can also improve the reliability of write-back data caches without compromising performance.</p>
W. Zhang, "Computing and Minimizing Cache Vulnerability to Transient Errors," in IEEE Design & Test of Computers, vol. 26, no. , pp. 44-51, 2009.