The Community for Technology Leaders
RSS Icon
Issue No.02 - March/April (2009 vol.26)
pp: 34-43
Kai-hui Chang , Avery Design Systems
David A. Papa , University of Michigan, Ann Arbor
Igor L. Markov , University of Michigan, Ann Arbor
Valeria Bertacco , University of Michigan, Ann Arbor
<p>Invers is a fast incremental-verification system for physical-synthesis optimization that includes capabilities for error detection, diagnosis, and visualization. Using a new metric called the similarity factor, Invers can help engineers identify potential errors earlier in development. Invers employs traditional verification only when necessary to ensure completeness of the verification flow. It also provides an error visualization interface to simplify error isolation and correction.</p>
Kai-hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco, "Incremental Verification with Error Detection, Diagnosis, and Visualization", IEEE Design & Test of Computers, vol.26, no. 2, pp. 34-43, March/April 2009, doi:10.1109/MDT.2009.38
1. R.C. Johnson, "Future of Chip Design Revealed at ISPD," EE Times,17 Apr. 2008; http://www.eetimes.comshowArticle.jhtml?articleID=207400313 .
2. C.E. Leiserson and J.B. Saxe, "Retiming Synchronous Circuitry," Algorithmica, vol. 6, nos. 1-6, 1991, pp. 5-35.
3. "Conformal Finds DC/PhysOpt Was Missing 40 DFFs!" ESNUG (E-mail Synopsys Users Group) 464, item 4, 30 Mar. 2007.
4. I. Chayut, "Next-Generation Multimedia Designs: Verification Needs," 43rd Design Automation Conf. (DAC 06), ACM, 2006; .
5. Q. Zhu et al., "SAT Sweeping with Local Observability Don't-Cares," Proc. 43rd Design Automation Conf. (DAC 06), ACM Press, 2006, pp. 229-234.
6. J.-H.R. Jiang and R.K. Brayton, "On the Verification of Sequential Equivalence," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 6, 2003, pp. 686-697.
7. K.-H. Chang et al., "InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization," Proc. 8th Int'l Symp. Quality Electronic Design (ISQED 07), IEEE CS Press, 2007, pp. 487-492.
8. Berkeley Logic Synthesis and Verification Group, "ABC: A System for Sequential Synthesis and Verification," release 51205; abc.
9. M.S. Abadir, J. Ferguson, and T.E. Kirkland, "Logic Verification via Test Generation," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 7, no. 1, 1988, pp. 138-148.
31 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool