Issue No. 02 - March/April (2009 vol. 26)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2009.36
Yervant Zorian , Virage Logic
Consumer application chips are the technology drivers today. Their design and test require different types of optimizations to address, on the one hand, the technology challenges, and on the other, very high volume production. This will necessitate adopting emerging solutions to meet such requirements. Optimizing for high-volume production, low power, and shrinking sizes necessitates adequate trade-off analysis, along with technical and business decision making by management. Also, moving to new semiconductor technology nodes, such as 45 nm and 32 nm, can significantly affect the choices of suppliers.
This special issue discusses these requirements and demonstrates corresponding management decision criteria to make the right choices from a pool of alternate options for flows, methodologies, tools, and IP blocks. The leading managers of today's most complex nanometer chips summarize these emerging solutions and their economic impact. This issue is designed to provide the IEEE Design & Test readership with a unique opportunity to gain insights from leading managers in the industry and to learn state-of-the-art information to help make decisions where business and technology intersect.
This special issue is based on the Management Day of the 45th Design Automation Conference (DAC), held in summer 2008. The Management Day comprised a full-day program including presentations and panels. This D&T issue features a select set of four presentations from this DAC Management Day presented by top-level managers representing major independent device manufacturers, such as Intel and STMicroelectronics, in addition to some of the largest fabless companies, such as MediaTek and SanDisk. While the end application domains considered in these articles do vary from each other, the management and technological challenges have many similarities.
Low-power chips require multidimensional optimization, which necessitates adequate trade-off analysis and technical/business decision making by management. The first three articles in this special issue demonstrate examples of low-power chips using such optimization processes presented by leading managers, who will discuss today's emerging solutions and their economic impact. In the first article, "The Story behind the Intel Atom Processor Success," Brad Beavers describes critical management solutions adopted for developing Intel's Atom processor with a very challenging schedule. In "Case Study of a 65-nm SoC Design," Andrew Chang describes another set of solutions adopted by MediaTek, when designing high-volume chips for cellular telephones. In the third article, "Low-Power Design Solutions for Wireless Multimedia SoCs," Philippe Magarshack and Jean-Pierre Schoellkopf summarize today's most critical challenges observed, and best practices adopted, by the design teams for STMicroelectronics wireless chips.
Design and manufacturing flows and methodologies are directly impacted by the demand for high-volume SoCs with increasing performance and parallelism. Moving to new semiconductor technology nodes while producing in high volumes can significantly affect the choices and outcome. In the final article, "From Specification to High-Volume Production," Manuel d'Abreu enlarges the analysis scope to include back-end-manufacturing-related considerations too, including test, yield, and reliability. This article demonstrates management decision criteria to make the right choices from a pool of alternate options.
A new version of Management Day will be featured at the 46th Design Automation Conference (DAC) and held on 28 July 2009 in San Francisco. If you would like to expand on the content of this special issue, please consider attending this upcoming version of Management Day.
I would like to take this opportunity to thank the authors of this special issue for their willingness to share their valuable experiences with the IEEE Design & Test readership, and to express my appreciation to the Executive Committee of the Design Automation Conference for their support and encouragement to develop this material. Last but not least, I would like to thank the editorial team of Design & Test, and particularly EIC Tim Cheng, for their contribution and patience during the work on this special issue.
I hope you find the Managing Emerging SoC Development articles both informative and useful.
Yervant Zorian is vice president and chief scientist at Virage Logic, and he is an EIC Emeritus of IEEE Design & Test. He has an MSc in computer engineering from the University of Southern California, an executive MBA from the Wharton School of Business, University of Pennsylvania, and a PhD in electrical engineering from McGill University. He is a Fellow of the IEEE, and he founded and chairs the IEEE 1500 standardization working group for embedded-core test.