Issue No. 01 - January/February (2009 vol. 26)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2009.1
Timothée Levi , LIMMS, University of Tokyo
Jean Tomas , Bordeaux University
Noëlle Lewis , Bordeaux University
Pascal Fouillat , Ecole Nationale Supérieure d'Electronique de Bordeaux
This article presents a CMOS resizing methodology for analog circuits during a technology migration, with easy-to-apply scaling rules based on a simple MOS transistor model. The goals are to transpose a circuit topology from one technology to another while preserving the main figures of merit and to quickly calculate the new transistor dimensions.
analog design, design reuse, MOS technology, resizing methodology, technology migration
P. Fouillat, N. Lewis, J. Tomas and T. Levi, "A CMOS Resizing Methodology for Analog Circuits," in IEEE Design & Test of Computers, vol. 26, no. , pp. 78-87, 2009.