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Issue No. 01 - January/February (2009 vol. 26)
ISSN: 0740-7475
pp: 68-77
Wenjing Rao , University of Illinois at Chicago
Ramesh Karri , Polytechnic University of NYU
Alex Orailoglu , University of California, San Diego
ABSTRACT
This article presents a mathematical model and algorithm that address the problem of logic function mapping in a nanoelectronic environment. Enhancement techniques improve the algorithm's runtime by significantly cutting down on unnecessary backtracking processes.
INDEX TERMS
nanoelectronic system, crossbar, defect tolerance, reliability, logic synthesis, bipartite graph, logic function mapping, two-level logic, nanofabric
CITATION
Wenjing Rao, Ramesh Karri, Alex Orailoglu, "Logic Mapping in Crossbar-Based Nanoarchitectures", IEEE Design & Test of Computers, vol. 26, no. , pp. 68-77, January/February 2009, doi:10.1109/MDT.2009.14
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