Issue No.01 - January/February (2009 vol.26)
Wenjing Rao , University of Illinois at Chicago
Alex Orailoglu , University of California, San Diego
Ramesh Karri , Polytechnic University of NYU
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2009.14
This article presents a mathematical model and algorithm that address the problem of logic function mapping in a nanoelectronic environment. Enhancement techniques improve the algorithm's runtime by significantly cutting down on unnecessary backtracking processes.
nanoelectronic system, crossbar, defect tolerance, reliability, logic synthesis, bipartite graph, logic function mapping, two-level logic, nanofabric
Wenjing Rao, Alex Orailoglu, Ramesh Karri, "Logic Mapping in Crossbar-Based Nanoarchitectures", IEEE Design & Test of Computers, vol.26, no. 1, pp. 68-77, January/February 2009, doi:10.1109/MDT.2009.14