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Issue No. 05 - September-October (2008 vol. 25)
ISSN: 0740-7475
pp: 442-451
Lorenzo Pieralisi , STMicroelectronics
Michael Hübner , University of Karlsruhe
Antonio Marcello Coppola , STMicroelectronics
Matthias Kühnle , University of Karlsruhe
Riccardo Locatelli , STMicroelectronics
Antonio Deledda , University of Bologna
Florian Ries , University of Bologna
Jürgen Becker , University of Karlsruhe
Tommaso DeMarco , STMicroelectronics
Fabio Campi , STMicroelectronics
Claudio Mucci , University of Bologna
Giuseppe Maruccia , STMicroelectronics
ABSTRACT
This work focuses on the interconnect infrastructure, functionality, and capability of a heterogeneous reconfigurable SoC. This SoC integrates reconfigurable units of various granularity used as stream-processing elements. A network-on-chip (NoC) approach demonstrates benefits in scalability, flexibility, and runtime adaptivity for actual and future SoC designs. On a reference CMOS090 implementation, the described interconnect system works at the system frequency of 200 MHZ, sustaining the required runtime bandwidth for several application domains.
INDEX TERMS
heterogeneous processing, network on chip, reconfigurability, streaming, SoC
CITATION
Lorenzo Pieralisi, Michael Hübner, Antonio Marcello Coppola, Matthias Kühnle, Riccardo Locatelli, Antonio Deledda, Florian Ries, Jürgen Becker, Tommaso DeMarco, Fabio Campi, Claudio Mucci, Giuseppe Maruccia, "An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC", IEEE Design & Test of Computers, vol. 25, no. , pp. 442-451, September-October 2008, doi:10.1109/MDT.2008.150
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