CEDA has formed a standards committee to promote the development of standards in the EDA industry and to act as the administrator for the working groups under it, which will develop and maintain standards. Such standards are beneficial to IC designers and automation tool developers and users in this industry because they provide a mechanism for defining common semantics.
The committee is to be represented by EDA consortia, semiconductor companies, and associated standards groups, and governed by a chairman and a steering committee. The latter comprises the chairmen of the working groups under the standards committee, and may also include elected members, such as senior managers in EDA and representatives from consortia, the Design Automation Standards Committee (DASC), and other interested parties. In addition, the steering committee may select ex officio members to foster continuity and coordination with related groups and to exercise any other functions necessary (for example, secretary) to effectively administer the committee. Because this committee is just forming, things are changing at a very rapid pace. To stay updated, please visit http://grouper.ieee.org/groups/ceda.
Moreover, CEDA organized a panel session on EDA standards for the recent Electronic Design Process (EDP) Workshop (held April 2008 in Monterey, California), promoting the initial approaches taken by CEDA in this area.
Please contact Rohit Kapur (firstname.lastname@example.org) or John Darringer (email@example.com) for further information.
The 2008 Phil Kaufman Award for Distinguished Contributions to EDA will be presented this October at the 15th Annual Phil Kaufman Award dinner and ceremony in Santa Clara, California. (Nominations for this award were accepted until June 30.) This award, jointly sponsored by CEDA and the EDA Consortium, honors individuals who have made a demonstrable impact on the field of EDA in business, industry direction and promotion, technology and engineering, or education and mentoring. It was established in 1994 in honor of deceased EDA industry pioneer Phil Kaufman, who turned innovative technologies such as silicon compilation and emulation into businesses that have benefited electronic designers.
The 2007 award winner was Robert Brayton (Cadence Distinguished Professor of Electrical Engineering and Computer Science at the University of California, Berkeley), for his demonstrable impact on the field of electronic design through contributions in EDA.
Please contact Nanette V. Collins (firstname.lastname@example.org) for further information, and visit http://www.edac.org/about_kaufman_award.jsp.
International Conference on Computer-Aided Design
ICCAD is the world's premiere conference on electronic design technology and has served EDA and design professionals for the past 25 years by highlighting new challenges and breakthrough innovative solutions for IC design technologies and systems. This year's conference will be held 10-13 November in San Jose, California. With continued participation from around the world, including North America, Europe, and Asia, the conference has received nearly 500 technical paper submissions of very high quality.
"ICCAD continues to be the premiere and most selective conference devoted to technical innovations in design automation of devices, circuits, and systems," stated Sani Nassif, ICCAD 2008 general chair. "As the number of conferences and meeting options for professionals and academics continues to grow, ICCAD remains uniquely recognized as the place where the most in-depth and respected research work in EDA is presented. This year we are enhancing ICCAD by offering our global set of attendees the option of attending a number of colocated workshops to further drill down in specific areas, and a strong lineup of keynotes that reflects the future of the broader fields of design automation."
Outstanding broadening keynotes
Such progress comes in the wake of a very successful 2007 program, which included two well-received keynotes: one from Jeffrey Welser of the Nanoelectronics Research Initiative, and the other from John Kibarian of PDF Solutions.
This year, ICCAD will host Mary Lou Jepsen, founder and CEO of Pixel Qi, and formerly the founding CTO of the One Laptop per Child (OLPC) project. Jepsen brings a unique perspective on systems design as well as a future vision on what will likely drive tomorrow's personal electronics.
As the ICCAD ecosystem broadens, and the need for effective technical conferencing and networking soars in our industry, ICCAD has started an initiative to host a selected number of colocated workshops. Not only are these workshops related to the field of automated design, but they are also of the same caliber as the conference itself. These workshops will leverage the entire conference management infrastructure and allow attendees to add a focused one-day technical activity with minimal disruption to travel schedules.
For example, there will be a workshop at this year's conference on compact variability modeling. Process variation is emerging as a fundamental challenge to IC design with scaled CMOS technology. Hence, this workshop bridges the gap between traditional device-level conferences such as the International Electronic Device Meeting (IEDM) and EDA conferences such as ICCAD.
Please contact Sani Nassif (email@example.com) for further information, and visit the ICCAD website at http://www.iccad.com.
Survey on 3D-Silicon Integration
Three-dimensional ICs composed of vertically stacked active-layer circuits allow shorter interconnections. Such integration could eventually help move ICs further along the path of Moore's law. Although the concept of 3D integration was originally reported in the 1980s, only in recent years has the development of 3D tiered architectures enabled the creation of vertical interconnects. The greatest economic advantage of such architectures is higher yield. Smaller chips have higher yield and thus lower defect rates when fabricated. Consequently, one way to achieve higher yield is to partition a circuit into k smaller subcircuits, each fabricated and stacked, and then build a single larger chip containing all the subcircuits on the same die.
Forthcoming electronics systems require the integration of new functionalities on one chip, defining the new design paradigm adopted in the EDA community known as the SoC. As a result, the number of inputs and outputs is increasing; chip size is decreasing; and new functions (such as passives, microelectromechanical systems, optoelectronics, and RF) are becoming more integrated. Therefore, the trend is to move from 2D configurations to 3D stacking and then to 3D ICs in order to reduce package size and footprint, increase silicon efficiency, and have many short interconnects. More precisely, the key potential benefits of 3D ICs include power reduction, noise and jitter reduction, logical fan-out increase, performance improvement, functionality enhancement, and density increase.
Many different 3D construction methods have been proposed, but none has reached the maturity level to achieve its use in forthcoming nanometer-scale electronics. For this novel integration technology to become a real alternative for the semiconductor industry, several key challenges must be addressed, spanning different manufacturing aspects to design automation. Thus, collaborative work is needed between the
• manufacturing community to provide a reliable physical implementation and models,
• EDA community to provide efficient CAD algorithms and tools, and
• verification community to provide effective testing mechanisms to validate the produced 3D chips for processing and communication architectures of electronic circuits.
Please contact David Atienza (firstname.lastname@example.org) for further information.
CEDA conferences provide excellent opportunities for those interested in learning about the latest technical trends in electronic design and automation. If you are interested in participating or have an idea about new topics of interest for our conferences, please contact William Joyner (email@example.com), CEDA vice president of conferences.
3rd International Conference on Nano-Networks (Nano-Net)
15-17 September 2008
18th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)
10-12 September 2008
16th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC)
13-15 October 2008
Rhodes Island, Greece
Embedded Systems Week (ESWEEK)
19-24 October 2008
IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
10-13 November 2008
San Jose, California
Formal Methods in Computer Aided Design (FMCAD)
17-20 November 2008