Issue No. 04 - July-August (2008 vol. 25)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2008.91
Jan M. Rabaey , University of California, Berkeley
Sharad Malik , Princeton University
The ability to stay on pace with Moore's law has been critical in providing for exponentially increasing computation capabilities per unit cost, and thus regularly enabling new applications. Maintaining this pace has always been challenging, but the challenges loom even larger as we approach the physical and economic limits of technology scaling. The resulting stress already is causing many companies to move toward fabless and fablight business models, with increased emphasis on system-level design technology. Another observable trend is the decline of ASICs and the corresponding growth in programmable platforms. These changes challenge traditional design technologies such as test and verification, and their interaction with emerging issues related to variability, reliability, and migration to post-silicon devices. This article proposes a roadmap of potential solutions for the future, based on managing massive concurrency, increasing self-adaptivity and resiliency, and adopting new computation models.
Moore's law, scaling, design technology, post-silicon, roadmap, system-level design.
Jan M. Rabaey, Sharad Malik, "Challenges and Solutions for Late- and Post-Silicon Design", IEEE Design & Test of Computers, vol. 25, no. , pp. 296-302, July-August 2008, doi:10.1109/MDT.2008.91