Issue No. 04 - July-August (2008 vol. 25)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2008.106
Many experts in the semiconductor industry believe that CMOS will continue to shrink all the way down to 5 to 7 nm. Moreover, according to the 2007 International Technology Roadmap for Semiconductors, the industry should be at the 22-nm technology node by 2016. However, there has been an increasing gap between the amount of research needed to solve the problems identified in the ITRS and the total research dollars funded by all sources in the world. The semiconductor research funding from traditional sources has been dropping, resulting in a lack of critical mass on priority topics for long-term research and for investigation of radical alternative technologies.
To address this gap, the Semiconductor Industry Association, in collaboration with the US Department of Defense and Semiconductor Research Corp., established a joint research program known as the Focus Center Research Program in the late 1990s. This program not only offers adequate resources for selected critical areas but also helps provide critical mass and synergy among university researchers. Ten years after this program was founded, the five centers funded under this program have successfully evolved to become a major research resource for the semiconductor industry.
This issue of IEEE Design & Test focuses on one of the five centers within the FCRP, the Gigascale Systems Research Center (GSRC), which addresses systems architecture and design aspects of electronics systems in the late- and post-silicon eras. Six articles written by the center researchers provide an overview of the visions and their key research results. The opening article by Rabaey and Malik offers insights on the key challenges of design technologies and proposes a roadmap of potential solutions for the future. Each of the next four articles summarizes the research in one of the four center themes: managing massive concurrency, increasing self-adaptivity and resiliency, adopting new computation models, and developing a unified system-level design methodology. The sixth article characterizes the essential features of future dominant applications that can drive the design of future systems. In addition, this special issue includes a Perspectives article by John Zolper describing critical research needs in system-level design and the GSRC's role in meeting those needs, as well as three sidebars on related topics from industry leaders in the field.
This special issue also features a dynamic interview with Intel Chair Craig Barrett, who is generally considered to be the "father" of the FCRP. In this interview, Barrett describes what triggered the creation of this program and his vision on what it might accomplish. He also shares his views on how well the current incarnation matches his original vision and where he expects the program to go in the future. He further discusses the major challenges the industry must overcome in the next decade and the role universities will play in addressing those challenges. Highlights of this interview are also available on video, which you can access from our Web site ( http://www.computer.org/dt).
Finally, this issue of D&T includes a general-interest article that reviews several chip-cooling techniques and presents an alternative approach based on a digital-microfluidic platform that uses the electrowetting phenomenon for adaptive cooling.
We hope you enjoy this exciting issue. We welcome your feedback.
Editor in Chief
IEEE Design & Test