Issue No. 03 - May-June (2008 vol. 25)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2008.61
Kip Killpack , Intel
Suriyaprakash Natarajan , Intel
Arun Krishnamachary , Intel
Pouria Bastani , University of California, Santa Barbara
Fast time to market and high performance translate to improved profit margins in the microprocessor business. The microprocessor design flow first involves design and timing convergence, then several iterations of frequency pushes on silicon, and finally volume production and sale to the market. Inevitably, speed failures occur because of frequency pushes, and these are prioritized on the basis of severity. Practical aspects such as time-to-market requirements limit the magnitude of eventual frequency push based on the amount of failures that can be analyzed. The authors of this article have analyzed 56 speed failures to understand the underlying causes. Specifically, they have studied the effects of multiple-input switching, cross-coupling noise, and localized voltage droop. Understanding the causes of speed failures provides insight so that designers can develop design strategies for better power-performance tradeoffs.
cross-coupling noise, multiple-input switching, voltage droop, silicon debug, critical path, microprocessor, diagnosis, marginality
K. Killpack, P. Bastani, A. Krishnamachary and S. Natarajan, "Case Study on Speed Failure Causes in a Microprocessor," in IEEE Design & Test of Computers, vol. 25, no. , pp. 224-230, 2008.