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Issue No. 03 - May-June (2008 vol. 25)
ISSN: 0740-7475
pp: 216-223
First-silicon validation and debug require a labor-intensive engineering effort of several months and have become the least predictable and most time-consuming part of a new 90-nm chip's development cycle. Lack of adequate tools and automatic procedures is a big factor in this bottleneck. Other difficulties include nondeterministic operation and lack of time-specific expected values. This article presents a new approach that provides an efficient scalable solution to overcome these difficulties. The end results are a significant reduction of the silicon validation and debug time, and faster discovery and root-cause determination of integration problems, design bugs, and chip defects.
silicon validation, silicon debug, logic analysis, on-chip instrumentation, assertions, reconfigurable infrastructure, system validation
Miron Abramovici, "In-System Silicon Validation and Debug", IEEE Design & Test of Computers, vol. 25, no. , pp. 216-223, May-June 2008, doi:10.1109/MDT.2008.77
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