The Community for Technology Leaders

Effective silicon debug is key for time to money

Pages: pp. 204

Silicon debug and diagnosis attempt to locate and fix the root causes of failures upon identification of a chip that violates either a functional or timing specification. The diagnosis results are also useful for failure analysis and yield improvement. However, the tasks of silicon debug and diagnosis are becoming increasingly more challenging, and their costs continue to rise for complex SoCs. Even after engineers have spent enormous amounts of time and effort on verification and emulation before a chip is taped out, the chance that the fabricated chip will work is not high, owing to failure sources such as uncaught functional bugs, inaccurate modeling in the design phase, process variations, dynamic noise, and manufacturing defects.

Although in principle significant synergy exists between presilicon verification and postsilicon debugging and diagnosis, in practice their respective methodologies, tools, and tests are seldom shared. Presilicon verification often assumes a white-box model, in which every internal signal is accessible for observation. But postsilicon debugging must follow a black-box model, in which the accessibility and observability of internal signals are very limited. Therefore, exploring ways to leverage the efforts, knowledge, and tests of presilicon verification for postsilicon debug can help reduce overall product cost and time to market.

The IEEE Design & Test editorial board has dedicated this issue to exploring silicon debug and diagnosis. Seven articles, selected from a large pool of high-quality submissions, examine various issues within this broad subject area. The topics covered include an overview of debug techniques for embedded-system functionality, an approach to in-system silicon validation, a case study on debug speed failures in microprocessors, a discussion on statistical-learning techniques to diagnosis, a survey of diagnosis techniques for scan chains, another survey on physical techniques facilitating chip-backside debug, and an overview of five debug standardization activities. I'd like to take this opportunity to thank our guest editors, Erik Jan Marinissen and Rob Aitken, for their great job in putting together this very strong and timely issue.

This issue also includes a roundtable based on a special session from the 2007 Design Automation Conference on thousand-core chips. Organized by D&T Roundtables Editor William Joyner and jointly moderated by David Yeh and Li-Shiuan Peh, this roundtable summarizes four panelists' views on education, programming languages, operating systems, and design automation for supporting future multicore chips.

Finally, I encourage you to participate in a future D&T issue by either submitting your theme or nontheme manuscript or by serving as a guest editor for a special theme issue. To submit your special-issue proposal for evaluation by our editorial board, please see our Web site ( Please also feel free to contact me directly for additional information or clarification.



Tim Cheng

Editor in Chief

IEEE Design & Test

54 ms
(Ver 3.x)