, University of Minnesota
Pages: pp. 194-195
Design for Manufacturability and Yield for Nano-Scale CMOS, by Charles Chiang and Jamil Kawa (Springer, 2007, ISBN: 978-1-4020-5187-6, 254 pp., $119.00).
One of the wonders of the Mead-Conway revolution was in providing a clean break between the design process and manufacturing. Circuits could neatly be represented by stick diagrams, and the separation requirements between features on a die could be captured by a set of design rules. In nanoscale CMOS technologies, this division between design and manufacturing is no longer as simple. In the modern area, subwavelength lithography issues and random variations have created headaches for designers. Fortunately, engineering ingenuity provides a remedy: design for manufacturability. DFM is a rapidly growing field that uses design techniques to improve manufacturing yield. However, as with many cures, this too has side effects: the dilution in the interface between design and manufacturing implies that today, to build a circuit with enhanced yield, a designer must know more about manufacturing than ever before. The first step to embracing yield considerations is to learn about them, and Design for Manufacturability and Yield for Nano-Scale CMOS, by Charles Chiang and Jamil Kawa, portrays the landscape of this area in an excellent way. The book describes methods for modeling variations, optimizing them, and learning to design around them when they occur—as they inevitably must.
An introductory chapter orients the reader by describing the issues involved in DFM and design for yield (DFY). This includes a basic overview of manufacturing advances that motivate the material in this book, including subwavelength lithography and new materials such as copper and low-K and high-K dielectrics. The remainder of the book covers failures and variations caused by phenomena such as random defects, subwavelength lithography, and chemical-manufacturing polishing (CMP), and discusses yield enhancement techniques to overcome these problems.
Chapter 2 begins with a description of the effects of random defects and their contribution to circuit failure. These defects can cause wires to be open or short circuited, or change the threshold voltage or mobility of a transistor. They are caused by particles in the photoresist, particles in the materials to be removed or added, or defects in the crystal structure. A thorough presentation of the theory of critical area for spot defects is provided. This includes analytical methods, whose roots lie in work that is a few decades old, and goes up to more recent work for critical area analysis and optimization.
Since about the 0.25-micron node, the industry has used subwavelength lithography, where the resolution of features printed on a circuit has been smaller than the wavelength of light. Chapter 3 presents a description of DFM and DFY issues related to lithographic issues, specially tailored for a designer or CAD engineer with no specific knowledge of optics. This begins with an overview of the root causes of the problem, then presents the concepts of resolution enhancement technology (RET) and optical proximity correction (OPC). The reader is capably led through an alphabet soup of terminology, ranging from optics techniques—for example, off-axis illumination (OAI) and double-dipole lithography (DDL)—to DFM methods that use subresolution-assist features (SRAF) and various types of phase-shift masks (PSMs). Finally, techniques for lithography-aware routing, verification, and litho-hotspot detection are described.
Another aspect of DFM is related to yield loss during the CMP process, when the surface of the partially manufactured die is smoothed for enhanced planarity. The achievable planarity in this step can be enhanced via uniformity in design; however, most designs are not especially uniform at the outset. Therefore, planarity must be enforced via metal fills. Chapter 4 first describes the technology issues related to building copper interconnects and measuring planarity through modeling and simulation, then the CMP process, and finally a survey of methods for rule- and model-based dummy fill insertion.
Chapter 5 discusses variability and parametric yield, including the root causes of variability and how they affect device and interconnect parameters. This leads into the next chapter, which discusses DFY techniques. The following two chapters provide an overview on statistical static-timing analysis (SSTA) methods to determine the probabilistic distribution of circuit delays, post-silicon methods for overcoming these problems using adaptive body biases and adaptive supply voltages, and yield prediction techniques.
The overall structure of this book is well thought out and logical, and the reader who peruses it will be rewarded with an excellent view of the field. The illustrations supplement the text nicely, and the pictures are a truly valuable aid to understanding concepts that might be unfamiliar to most designers. The book has some unfortunate features (or bugs): the style and quality of writing is a bit choppy, the ideas presented within the book do not always flow smoothly, and there are several typographical errors that could have been removed through more careful proofreading. In addition, its utility as a reference is somewhat diminished by the fact that it does not have an index at the end. On the other hand, the mix of breadth and depth provided by the book is very appropriate, and the authors have made a serious effort to present a complete and representative view of the field. Several references are provided at the end for the curious reader to follow up on. A reader who is more concerned about the content can easily overcome these minor hurdles, and use the book as a good starting point to learn about DFM. On balance, I find it a welcome and useful addition to my own bookshelf.