Issue No. 02 - March-April (2008 vol. 25)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2008.56
Laung-Terng Wang , SynTest Technologies
Xiaoqing Wen , Kyushu Institute of Technology
Shianling Wu , SynTest Technologies
Zhigang Wang , Cisco Systems
Zhigang Jiang , SynTest Technologies
Boryau Sheu , SynTest Technologies
Xinli Gu , Cisco Systems
This article describes a test compression technology, called VirtualScan, which achieves scan test cost reduction by inserting a small combinational broadcaster and compactor into the original circuit under test (CUT). In addition, one-pass ATPG takes into account all constraints imposed by the VirtualScan compression architecture, and generates compression test patterns in the same manner as a conventional full-scan ATPG. The simplicity of the combinational-logic-based compression technology further allows for flexibility in addressing unknown (X) values and fault-aliasing effects, through either an enhanced ATPG algorithm or enhanced compactor logic.
ATPG, scan testing, test compression, combinational broadcaster, combinational compactor, low-power testing, fault diagnosis
X. Gu et al., "VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG," in IEEE Design & Test of Computers, vol. 25, no. , pp. 122-130, 2008.